This invention pertains generally to a phase-lock loop control loops, and, in particular, to a technique for improving the transfer characteristics of a wide band phase comparator logic network intended for use at high frequency with close phase control.
As is known, emitter coupled logic (ECL) phase detectors have been successfully utilized to close phase lock loops operating at intermediate frequencies of 5 to 30 MHz. One known ECL phase detector manufactured by Motorola Company and designated the Model No. 12040 phase comparator logic network, operates to compare the relative timing between positive-going transitions of a reference (R) and a signal (S) input waveform to generate either an up (U) or down (D) output signal having a duty cycle proportional to the phase difference between the R and S input waveforms. In practice, an operational amplifier then is used to combine and integrate the output signal from the phase detector to provide the requisite control signal for the controlled oscillator in the loop. Although networks such as the Motorola 12040 phase comparator logic network have been successfully utilized to control loops in the frequency range of 5 to 30 MHz when any known network is operated at higher frequencies (say in the order of 100 MHz), propagation delays within the network cause gain distortion, especially in the critical region where there is little, if any, phase difference between a reference signal and the signal out of the controlled oscillator. Such gain distortion varies from network to network and, unless compensated for, will result in an unacceptable increase in the level of phase modulated noise sidebands which result in unsatisfactory operation.